1. FIELD OF THE INVENTION
The present invention relates to an integrated memory array of EPROM cells organized in a "tablecloth" arrangement and to the process for fabricating it.
In the fabrication of a memory matrix, particularly of EPROM cells, an important goal is to maximize cell density in order to improve performance and exploit better the available semiconductor area. This imposes the development and adoption of advanced technologies, especially in the photolithographic field, with the ability to define patternings with submicrometric dimensions, e.g. 0.8 .mu.m. Notwithstanding improvements in the photolithographic area it is increasingly becoming difficult to compact the cells any further, therefore R & D efforts have been oriented toward new types of architecture Which may help to increase cell density.
2. DESCRIPTION OF THE PRIOR ART
In the specific field of EPROM cells, a greater density could be achieved by passing from a conventional configuration with pairs of control gate lines running over and aligned with floating gate structures and with parallel source lines running therebetween, while drain contacts are realized between the control gate lines of each pair, to a so-called "tablecloth" configuration using parallel and alternately arranged source and drain lines with floating gates formed between adjacent source and drain lines, and control gate lines parallel among each other and running perpendicularly to said source and drain lines, over and aligned with said floating gates.
This latter configuration is described in the prior U.S. patent application Ser. No. 783,650, now U.S. Pat. No. 4,792,925, filed on Oct. 3, 1985, and has advantages in respect to a traditional configuration in terms of an easier dimensional control of the patterning steps and a remarkable degree of cell density can be achieved. An accompanying decodification complexity for addressing individual cells has played against a commercial exploitation of this new configuration.
In order to overcome this drawback, in a subsequent U.S. patent application Ser. No. 369,132, now abandoned, filed on June 21, 1989, a modified "tablecloth" EPROM cell array was described. This array had spaced, parallel and alternately arranged source and drain lines, floating gate areas realized between said source and drain lines and control gate lines parallel among each other and running perpendicularly to said source and drain lines and over said floating gate areas and was characterized by comprising isolating strips of field oxide running parallel to and alternately with said spaced, parallel source and drain lines in order to divide the matrix into electrically isolated groups of cells comprising two drain lines and a source line running therebetween and spatially connected by floating gate areas over which relative control gate lines run.
In this way individual access to single cells was made possible by a conventional decodification.
The division of the cells in isolated groups determined by the field oxide strips made possible a positive selection of one cell at the time, by applying a certain voltage to the appropriate drain and control gate lines while grounding all the source lines of the matrix. The field oxide prevented the voltage applied to the selected drain line to affect other cells associated to the same control gate line and therefore singled-out the addressed cells. In a global production economy of this kind of memories, the fabrication process itself has a remarkable importance from the point of view of the yield and reliability of the products as well as from a non-negligeable point of view of the cost of production.